Things I’ve discovered and considered relevant at the time.

Access Keyword

One way to handle variable length strings is to use access pointers as defined here: http://vhdl.renerta.com/mobile/source/vhd00001.htm

Assigning a new string goes as follows.

type str_ptr is access string;
variable myString str_ptr;
myString := string'("hello world");

Conditional Writeline

or how to handle lines written as debug messages in case they’re not needed. We don’t want to create memory leaks, don’t we?

variable lineOut : line;
if someBoolean then
  write(fh, lineOut);
  else
    deallocate(lineOut);
    end if;

The source is here.

Delay Model

The VHDL delay model has a few quirks when it comes to delayed assignments. If in the following examples

q1<=r nor nq after 1ns;
q2<=transport r nor nq after 1ns;

nq has a spike shorter than 1 nanosecond, only q2 will see the change. A more thorough explanation can be found here.

VHDL bits and pieces

Things I’ve discovered and considered relevant at the time.

Access Keyword

One way to handle variable length strings is to use access pointers as defined here: http://vhdl.renerta.com/mobile/source/vhd00001.htm

Assigning a new string goes as follows.

type str_ptr is access string;
variable myString str_ptr;
myString := string'("hello world");

Conditional Writeline

or how to handle lines written as debug messages in case they’re not needed. We don’t want to create memory leaks, don’t we?

variable lineOut : line;
if someBoolean then
  write(fh, lineOut);
  else
    deallocate(lineOut);
    end if;

The source is here.

Delay Model

The VHDL delay model has a few quirks when it comes to delayed assignments. If in the following examples

q1<=r nor nq after 1ns;
q2<=transport r nor nq after 1ns;

nq has a spike shorter than 1 nanosecond, only q2 will see the change. A more thorough explanation can be found here.